Strained Silicon On Insulator (sSOI)

M. Reiche and S. Christiansen


Tensile strain in silicon is usually created by the pseudomorphic silicon growth on relaxed SiGe layers. A variety of methods, such as graded SiGe buffers [1] and He implantation into SiGe [2] were applied to form relaxed SiGe, but the involvement of dislocations in these processes poses challenges for device application, such as control of leakage current and device yield. The defect density can be reduced, but not eliminated, by using thick SiGe layers. There have been numerous efforts to combine strained silicon with SOI structures to explore SOI-specific benefits, such as dual-gate possibility, reduced parasitic capacitance, and improved device scaling.
Langdo et al. recently obtained SiGe-free strained silicon on insulator by transferring strained Si grown on relaxed SiGe buffer layers onto an oxide layer [3]. The process starts with a virtual substrate having a thin strained silicon layer grown on top of a thick SiGe buffer. The virtual substrate was bonded to an oxidized silicon wafer. Finally, the Si handle wafer and SiGe layer of the virtual substrate were removed by bonding and etch back. A further improvement of the process was obtained by using layer transfer techniques combining hydrogen-induced layer splitting with wafer bonding [4].
Within the TESIN project virtual substrates are used characterized by a strained silicon layer grown on a thin, about 400 nm thick SiGe buffer layer relaxed by He implantation (Fig. 1). The advantages of these substrates are very smooth surfaces (no additional CMP steps are required for wafer bonding) and re-usable virtual substrates. Hydrogen implantations were performed at energies resulting in the peak of the implantation induced damage close to the interface between the SiGe and the underlying Si substrate. The wafers were bonded and subsequently annealed in order to increase the bonding strength and to initiate the layer splitting ((Fig. 2). Finally, the SiGe layer was removed by selective wet-chemical etching [5].

 Fig. 1 schematic presentation of the formation process of strained silicon on a thin SiGe substrate layer relaxed by helium implantation [2].



Fig 2: schematic presentation of the process flow



[1] E.A. Fitzgerald, Y.-H. Xie, D. Monroe, P.J. Silverman, J.-M. Kuo, A.R. Kortan, F.A. Thiel, B.E. Weir, and L.C. Feldman, J. Vac. Sci. Technol. B 10, 1807 (1992). [2] B. Holländer, S. Lenk, S. Mantl, H. Trinkaus, D. Kirch, M. Luysberg, T. Hackbarth, H.-J. Herzog, P.F.P. Fichtner, strain relaxation of pseudomorphic Si1-xGex/Si(100) heterostructures after hydrogen or helium ion implantation for virtual substrate fabrication, Nucl. Instrum. & Meth. B 175-177, 357-367 (2001)
[3] T.A. Langdo, M.T. Currie, Z.-Y. Cheng, J.G. Fiorenza, M. Erdtmann, O. Braithwaite, C.W. Leitz, C.J. Vineis, J.A. Carlin, A. Lochtefeld, M.T. Bulsara, I. Lauer, D.A. Antoniadis, M. Somerville, Strained Si on insulator technology: from materials to devices, Solid-State Electron. 48, 1357-1367 (2004)
[4] B. Ghyselen, J.-M. Hartmann, T. Ernst, C. Aulnette, B. Osternaud, Y. Bogumilowicz, A. Abandie, P. Besson, O. Rayssac, A. Tiberj, N. Daval, I. Cayrefourq, F. Fournel, H. Moriceau, C. Di Nardo, F. Andieu, V. Paillard, M. Cabié, L. Vincent, E. Snoeck, F. Cristiano, A. Rocher, A. Ponchet, A. Claverie, P. Boucaud, M.-N. Semeria, D. Bensahel, N. Kernvez, C. Mazure, Solid-State electron. 48, 1285-1296 (2004)
[5] I. Radu, M. Reiche, C. Himcinsci, R. Singh, S. Christiansen, U. Gösele, Comparison of SiGe virtual substrates fort he fabrication of strained silicon on insulator (sSOI) using wafer bonding and layer transfer, ECS Transactions 3 (7), 317-324 (2006)

back  |  print  |  to top