Local Strain (Process-Induced Strain)

Electron and hole mobilities respond to mechanical stresses in different ways. For MOSFETs with the [110] channel orientation on {001}-oriented silicon substrates, tensile strain along the [110] direction improves electron mobility but degrades hole mobility. Therefore, to improve both the electron mobility in n-channel MOSFETs (NMOS) and the hole mobility in p-channel MOSFETs (PMOS), the introduction of strain in the transistor channel needs to employ different approaches for NMOS and PMOS.

Advanced CMOS processes contain different process-induced stressors. These are mainly overlayers, embedded stressors, and stress memorization techniques (Fig. 1). Overlayers are typically stressed nitride layers deposited after salicidation of the source/drain and gate. Tensile overlayers are deposited over NMOS and compressive overlayers are deposited for

Fig. 1: Schematic representation of local stressors (process-induced stressors) in SOI CMOS. Tensile strain in NMOS is obtained by tensile overlayers and various stress memorization techniques. Compressive strain in PMOS is induced by compressive overlayers and embedded SiGe.

PMOS. The strain in the channel region depends on the intrinsic stress of the layer, thickness of the layer, and device dimensions. Using tensile and compressive layers (dual stress liner, DSL) a significant hole mobility enhancement of 60% was achieved [1]. Furthermore, important parameters of SOI CMOS devices, such as effective drive current enhancement, were proved in different 45 nm technologies.

Stress memorization techniques (SMT) typically involve a nitride capping layer and an additional annealing step. They increase NMOS drive current and degrade the PMOS transistor.

Embedded SiGe layers (eSiGe) are widely used in PMOS transistors. Caused by the larger lattice constant of SiGe, compressive strain is induced in the channel. Currently this technique is improved by combining SiGe and SiC layers and mixtures of both [2,3].

The integration of the different stressors into advanced CMOS technologies results in increasing device performance required by the ITRI road map [4].


1.H.S. Yang, R. Malik, S. Narasima, Y. Li, R. Divakaruni, P. Agnello, S. Allen, A. Antreasyan, J.C. Arnhold, K. Bandy, M. Belyansky, A. Bonnoit, G. Bronner, V. Chan, X. Chen, Z. Chen, D. Chidambarro, A. Chou, W. Clark, S.W. Crowder, B. Engel, H. Harifuchi, S.F. Huang, R. Jagannathan, F.F. Jamin, Y. Kohyama, H. Kuroda, C.W. Lai, H.K. Lee, W-H. Lee, E.H. Lim, W. Lai, A. Mallikarjunan, K. Matsumoto, A. McKnight, J. Nayak, H.Y. Ng, S. Panda, R. Rengarajan, M. Steigerwalt, S. Subbanna, K. Subramanian, J. Sudijono, G. Sudo, S-P. Sun, B. Tessier, Y. Toyoshima, P. Tran, R. Wise, R. Wong, I.Y. Yang, C.H. Wann, L.T. Su, IEDM Techn. Digest, p. 1075 (2004).


2.Y.C. Yeo, Semicond. Sci. Technol. 22, S177 (2007).


3.M. Wiatr, Advanced SOI CMOS transistor technology for high performance microprocessors, MAR08 Meeting of the American Physical Society, Abstr., March 10-14, New Orleans.


4.International Technology Roadmap for Semiconductors, Update 2006.



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