Size-controlled Si Nanocrystals


Charge Storage:

M. Zacharias, T.Z. Lu, and D. Hiller


MOS structures containing multilayers of Si NCs were fabricated by thermal evaporation and high temperature annealing for crystallization. The TEM investigation shows separated spherical Si NCs embedded in up to three layers. The characteristic multi-level charge storage was demonstrated by a family of C-V hysteresis. The steps in the flatband shift show that the charge stages are corresponding to the charging of the respective number of layers. Retention measurements are performed which shows a good stability of the programming states. Our results not only show a good memory capability of such multi-layer Si NC devices, but also the feasibility of memory devices having a multi-bit/cell storage behavior.



Electrical behavior of single-layer Si nanocrystals embedded in SiO2 matrix




Current-voltage, capacitance-voltage, and conductance-voltage characterizations are realized for MOS structure containing a single layer of 4 nm Si nanocrystals. Electron trapping, storing, and de-trapping in silicon nanocrystals were observed.  T.Z. Lu et al. Appl. Phys. A 80 (2005) 1631.



Multilevel charge storage in multi-layered Si nanocrystals 




The feasibility of multilevel charges is investigated using layered ~4 nm Si nanocrystals in a MOS structure. Charge storage is observed by successive charging of a varied number of Si nanocrystal layers in the floating gate. The feasibility for using such a stack structure in multibit/cell nonvolatile memories is demonstrated.  T.Z. Lu et al. Appl. Phys. Lett. 87 (2005) 202110.



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